A Novel Iddq Scanning Technique For Pre-Bond Testing

Electronic Stacked integrated circuits presents many advantages like short latency, low power consumption, and immense amount of bandwidth delivered by Through Silicon Vias (TSV). However, these circuits present many test issues, designer must ensure that each of individual die layer is designed to be testable before bonding take places. In this paper we propose a novel technique of Design for testability (DFT) architecture that can be used in pre-bond testing to identify defective Die’s from the wafer. The main idea is to measure the variation of circuit’s current consumption in order to detect defective IC’s. A new architecture of a dual mirror built in current sensor is proposed. SPICE simulation and logic synthesis are performed to prove the efficiency of the proposed design.